1. Field of the Invention
The present invention relates to a sigma-delta modulator, and more particularly, to a multi-bit sigma-delta modulator and a digital-to-analog converter for a sigma-delta modulator that are capable of implementing a five-level output through one capacitor in single ended form. The digital-to-analog converter of the present invention may be extendible to a differential operation. Hereinafter, a configuration based single ended form will be described for convenience.
2. Discussion of Related Art
Generally, a sigma-delta modulator includes two blocks: an integrator for integrating a difference between an input analog signal and an output signal of a digital-to-analog converter (DAC) according to a code of an analog-to-digital converter (ADC), and the ADC for converting an analog output of the integrator into a digital signal.
FIG. 1A is a block diagram illustrating a general first-order sigma-delta modulator, and FIG. 1B illustrates the first-order sigma-delta modulator of FIG. 1A as a linear model.
As illustrated in FIGS. 1A and 1B, the general first-order sigma-delta modulator is configured with a negative feedback, and the ADC in the first-order sigma-delta modulator may be replaced with a model in which quantization noise is added. An output (Vout) that is the result of interpreting the general first-order sigma-delta modulator using the linear model of FIG. 1B is given by Formula 1.
[Formula 1]
      V    ⁢                  ⁢    out    =                    1                  s          +          1                    ⁢      V      ⁢                          ⁢      in        +                  s                  s          +          1                    ⁢      e      
As shown in Formula 1, the output (Vout) indicates a low-pass characteristic with respect to an input (Vin), and indicates a high-pass characteristic with respect to the quantization noise (e). Therefore, if a low pass filter is used to produce an output of the sigma-delta modulator, the output may have low quantization noise and, accordingly, a high signal-to-noise ratio (SNR).
The SNR of the sigma-delta modulator having the above-described characteristics is determined by the number of integrators (L), which may be indicated as an order of the modulator, the number of ADC bits, and an oversampling ratio, which is a ratio of sampling frequency range to signal frequency range. The maximum SNR is given by Formula 2.
[Formula 2]
      SNR    ⁡          (      dB      )        =      1.76    +          20      ⁢                          ⁢              log        ⁡                  (                                    2              B                        -            1                    )                      +          10      ⁢                          ⁢      log      ⁢                          ⁢      M        +                  20        ·        L        ·        log            ⁢                          ⁢      M        +          20      ⁢                          ⁢      log      ⁢                                                  2              ⁢              L                        +            1                                    π          L                    
As shown in Formula 2, to increase the SNR, the order, the number of ADC bits, or the oversampling ratio should be increased.
However, the method of increasing the order has a problem regarding stability, and reduces an available signal range. Also, since the method of increasing the oversampling ratio requires a high sampling frequency, a circuit should operate at high speed. Therefore, the above-mentioned methods are not suitable for the low-voltage, high-speed sigma-delta modulator.
Meanwhile, the number of ADC bits in the high-resolution, high-speed, and low voltage sigma-delta modulator may be increased. However, when the number of ADC bits is increased, the performance of the sigma-delta modulator may be affected by linear characteristics of the DAC in a negative feedback loop.
FIG. 2 illustrates an integrator in the form of a commonly used switched capacitor also performing a function of a B-bit DAC. In FIG. 2, mismatching of a DAC capacitor 10 directly affects DAC linear characteristics. Since the mismatching of capacitors 11 through 12 is determined by a process characteristic, there is a limit to improving the mismatching characteristic. Accordingly, the performance of the high-resolution, high-speed, and low voltage sigma-delta modulator may deteriorate due to the capacitor mismatching.
Therefore, to solve a problem regarding the DAC capacitor mismatching, various methods such as Random Averaging, Clocked Averaging (CLA), Individual Level Averaging (ILA), Data Weighted Averaging (DWA), etc., have been suggested. However, these methods require a lot of complex digital circuits, and under certain conditions the performance of the DAC may deteriorate.